The Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60 GHz frequency range (57 to 64 GHz). Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS) or Silicon-Germanium (SiGe) technology to form the dice in these designs. At 60 GHz, short on-chip metallic traces translate to inductance values that impact the design of these high frequency circuits. The approximate parasitic inductance of metallic trace in an integrated circuit at this frequency is of the order of 1 pH per micrometer of trace length (2-4 um trace width and 0.85-3 um thickness). At 60 GHz, a typical inductor has an inductance on the order of about 50 to 120 pH and, for one example case, occupies a die area of about 100 um on a side
At these high frequencies (˜60 GHz), there are essentially two approaches to transferring signals between stages. Both approaches use reactive devices. These approaches are known as “AC coupling” and “transformer coupling.” The reactive devices that are used in these two approaches tend to use up more die area than the active devices within the stage themselves.
In the “AC coupling” approach, (for example, see: Chinh H. Doan, Sohrab Emami, Ali M. Niknejad, Robert W. Brodersen, “Design of CMOS for 60 GHz Applications”, Session 24.4, Feb. 18, 2004, IEEE International Solid-State Circuits Conference, San Francisco, Calif.) the signals between stages are transferred through a series capacitor coupled between a first stage and the next stage. The capacitor blocks the DC operating voltages of the first stage from affecting the DC operating conditions of the next stage. This technique allows each stage to be DC biased independently of each other; however, the AC component of the signal is transferred between stages through the capacitor. Forming this capacitor on an integrated circuit also introduces an undesired and unavoidable parasitic capacitance to ground, power and die (substrate). This reduces the efficiency and increases the power dissipation of the “AC coupling” approach. A typical coupling capacitor at 60 GHz can range from 200 fF to 500 fF and, for one example case, would have a dimension of 40 um by 40 um.
The second approach uses “transformer coupling” (for example, see: Wei L. Chan, John R. Long, Marco Spirito, John J. Pekarik, “A 60 GHz-Band 1V 11.5 dBm Power Amplifier with 11% PAE in 65 nm CMOS”, Session 24.4, Feb. 11, 2009, IEEE International Solid-State Circuits Conference, San Francisco, Calif.) between stages to transfer the signals between the first stage and the next stage. Transformers have large dimensions on a die and are typically used in a balanced signal configuration. Transformers typically have a large parasitic capacitance. The active devices and balanced networks resonate out the parasitic capacitance of the transformer. However, transformers suffer skin loss, coupling loss and die (or substrate) loss. The balanced configuration requires the generation of two signals 180° out of phase with each other. This increases the power dissipation of this approach since there are twice the stages over that of the “AC coupling” approach. The metallic traces form the lower and upper coils of the transformer that are separated by an oxide and typically overlay one over the other to increases the coupling coefficient (˜0.9) in the transformer. The lower side of the lower coil, the top side of the upper coil and the sides of the coils have stray capacitance. This reduces the efficiency and increases the power dissipation of the “transformer coupling” approach. One typical transformer at 60 GHz could have a dimension of 80 um by 80 um. The transformers uses about 4 times more die area then the coupling capacitors.
One of the disadvantages of the coupling capacitor and coupling transformer methods is their very large physical size, which translate to larger die area and increased cost. Also, due to the large area of these reactive components, the length of the trace to interconnect the first stage to the next stage through the reactive component increases. Since each micrometer of trace has 1 pH of inductance and the dimensions of the reactive devices are on the order of a 100 um length, the parasitic inductance and capacitance could significantly alter the desired load inductance and capacitance.
In addition to these disadvantages, CMOS foundries typically do not provide models or guarantee that the coupling capacitor and transformer modeling for circuits operating more than 20 GHz. This presents a very significant challenge and difficulties to companies without a modeling group and high frequency measuring equipment. This requires that the Radio Frequency (RF) designer to carefully study and analyze the physical layout of their circuit in a given technology without the advantage of these models or the behavior of the circuit at 60 GHz. The additional time needed to perform this analysis increases the length of time to generate the final mask levels for the given technology (known as “tapeout”) and opens the potential for lost revenue.